Design requirements: increase the read and write function of the encoder EEPROM
Hardware version: control board (ARM and FPGA parallel communication ) Tamagawa encoder (17bit and 23bit only),
Software version: ARM and CPLD use parallel communication, 8bit address, 16bit data (the current loop cycle is a data cycle)< /p>
Design ideas:
- The current loop cycle is a communication cycle, and the parallel port address EEPROM is added, which is used to write the encoder EEPROM address and data, and the specific data See the distribution below;
- Because the address to be written is 16 bits, and the data length corresponding to each address is not equal, the address is re-expanded with 8bit data;
- Because every EEPROM An 8-bit address stores a data format of 8-bit data, so the parallel port 16-bit data is just divided into data group (EDF) and address group (ADF). EDF is the upper eight bits. When reading the address, only the eighth bit ADF is taken. The lower data in the PD group corresponds to the lower address;
- Figures 1, 2 are the specific data structure of EEPROM, which is different from the data structure of reading the encoder position (Figure 3), so the following rules are added: A write or command requires 8bit address (ADF) and 8bit data (EDF) (read command only requires ADF). Both ADF and EDF of the parallel port are transferred from the 16 data of the parallel port, and the corresponding data address of the parallel port is EEPROM. The data is returned from the original address ABS_CF_SF, ABS_DF0_DF1, the specific operation is shown in Figure 4 and Figure 5; Introduction
Alignment: left” align=”left”>
Alignment: left”> Picture 2: Reading encoder EEPROM data structure
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Figure 3: Data structure of reading encoder position
When writing EEPROM specifically: EEPROM 4 p>
Figures 5 :The specific operation of reading the parallel port of EEPROM