VHDL – Error: XST: 827 = Signal Count Uncosystem, Synchronous Description Error

elsif (updownpassenger = '1') then 

process(clock, async_reset) - nothing else should go in the sensitivity list
begin
 - never put anything here
 if async_reset ='1' then - or '0' for an active low reset
 - set/reset the flip-flops here
 - ie drive the signals to their initial values
 elsif rising_edge(clock) then - or falling_edge(clock) or clk'event and clk='1' or clk'event and clk='0'
 - put the synchronous stuff here
 - ie the stuff that happens on the rising or falling edge of the clock
 end if;
 - never put anything here
end process;

process(clock) - nothing else should go in the sensitiv ity list
begin
 - never put anything here
 if rising_edge(clock) then - or falling_edge(clock) or clk'event and clk='1' or clk'event and clk ='0'
 - put the synchronous stuff here
 - ie the stuff that happens on the rising or falling edge of the clock
 end if;
 - never put anything here
end process;

process(all inputs in the sensitivity list) - an 'input' is a signal either on the LHS of an assignment or a signal that is tested
begin
 - combinational logic (with complete assignment and no feedback)
end process;

I tried to simulate an elevator, but I got an error

ERROR:Xst:827 = Signal count cannot be synthesized , bad synchronous description

I am following the code from this source [https://www.youtube.com/watch?v=i03_-NMwmDs], because I am very similar, (I have 7 layers, also There are two elevators). At first I was working on the code mentioned in the video, and then I will implement more than two elevators in this simulation.

Thanks in advance.

Thanks in advance.

p>

library ieee;
use ieee.std_logic_1164.all;
us e ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity elevator is
port (clk: in std_logic;
sensors1: out std_logic:= '0'; --sensors at each level for elevator 1
a1, a2, a3, a4, a5, a6, a7: out std_logic; - for LED display at FPGA
insideopendoor, in1, in2 , in3, in4, in5, in1up, in2up, in3up, in4up, in5up, in5down, in4down, in3down, in2down, in1down: std_logic; - input request for each floor
opendoor: out std_logic; - from inside elevator 
closedoor: out std_logic); - from inside elevator
end elevator;

architecture sequence of elevator is

constant timedoorclose: integer := 3 ; 
constant timedoorclosed: integer := 2; 
constant time_nx_state: integer :=4;
signal demand: std_logic_vector(0 to 4) := "00000";
signal direction_of_elevator : integer range 0 to 2 := 0;
signal updownpassenger: std_logic := '0';
signal signalstatus: std_logic := '1';
type status is (L1, L2, L3, L4, L5);
signal pr_state, nx_state: status;

begin

main: process (clk, insideopendoor, in1 , in2, in3, in4, in5, in1up, in2up, in3up, in4up, in5up, in5down, in4down, in3down, in2down, in1down)
variable digit1: std_logic_vector (6 downto 0);
variable count: integer range 0 to (time_nx_state + timedoorclose + timedoorclosed);
variable bufferopendoor: std_logic;
variable position: integer range 0 to 4;
variable tempup: integer range 1 to 2 := 1; 
variable tempdown: integer range -4 to 4;

begin

if (clk'event and clk='1') then
 demand( 0) <= demand(0) or in1 or in1up or in1down;
 demand(1) <= demand(1) or in2 or in2up or in2down;
 demand(2) <= demand(2) or in3 or in3up or in3down;
 demand(3) <= demand(3) or in4 or in4up or in4down;
 demand(4) <= demand(4) or in5 or in5up or in5down;< br />
 case pr_state is 
 when L1 => position := 0;
 when L2 => position := 1;
 when L3 => position := 2;
 when L4 => position := 3;
 when L5 => position := 4;
 end case;

 for i in 1 to 4 loop
 if demand(i) ='1' then
 tempup := i-position;
 else null;
 end if;
 end loop;

 for i in 3 downto 0 loop
 bufferopendoor := '1' ;
 closedoor <= '0';
 count := 0;
 end loop; --


elsif (updownpassenger = '1') then
 if (count  opendoor <= '1';
 bufferopendoor := '1';
 elsif count <(timedoorclose + timedoorclosed) then
 opendoor <= '0';
 bufferopendoor := '0';
 else
 closedoor <= '0';
 end if;
 --else null; ------
--end if; ------

-----------part main--- --------------
count := count +1;
 if insideopendoor = '1' then
 opendoor<='1';
 bufferopendoor :='1';
 closedoor <= '0';
 count := 0;
 elsif (updownpassenger ='1') then
 if (count  opendoor <= '1';
 bufferopendoor := '1';
 closedoor <= '0';
 elsif (count <(timedoorclose + timedoorclosed)) then 
 opendoor <= '0';
 bufferopendoor := '0';
 closedoor <= '1';
 else
 closedoor <= '0';< br /> pr_state <= nx_state;
 if signalstatus = '1' then
 signalstatus <= '0';
 else
 signalstatus <= '1';
 end if; 
 count := 0;
 end if;
 else null; --
 end if;--

 case nx_state is
< br /> when L1 =>
 digit1 := "1111001";
 if demand(0) = '1' then
 demand(0) <= '0';
 else null;
 end if;

 when L2 =>
 digit1 := "0100100";
 if demand(1) = '1' then
 demand(1) <= '0';
 else null;
 end if;

 when L3 =>
 digit1 := "0110000";
 if demand(3) = '1' then
 demand(3) <= '0';
 else null;
 end if;

 when L4 => 
 digit1 := "0011001";
 if demand(3) = '1' then
 demand(3) <= '0';
 else null;
 end if;

 when L5 =>
 digit1 := "0010010";
 if demand(4) = '1' then
 demand(4) <= '0';
 else null;
 end if;
 when others => null;
 end case;

a1 <= digit1(0) ;
a2 <= digit1(1);
a3 <= digit1(2);
a4 <= digit1(3);
a5 <= digit1(4);< br />a6 <= digit1(5);
a7 <= digit1(6);
end if;
end process main;

step: process ( pr_state, signalstatus)

begin

case pr_state is
--end if;

when L1 => 
if (demand(0)='1') then
 nx_state <= pr_state;
 updownpassenger <= '1';
else 
 updownpassenger <= '0'; 
 if direction_of_elevator = 1 then
 nx_state <=L2;
 elsif direction_of_elevator = 2 then
 nx_state <= pr_state;
 else
 nx_state <= pr_state; 
 end if;
end if;

when L2 => 
if (demand(1)= '1') then
 nx_state <= pr_state ;
 updownpassenger <= '1';
else 
 updownpassenger <= '0';
 if direction_of_elevator = 1 then
 nx_state <= L3;
 elsif direction_of_elevator = 2 then
 nx_state <= L1;
 else
 nx_state <= pr_state;
 end if;
end if;

 when L3 => 
if (demand(2)= '1') then
 nx_state <= pr_state;
 updownpassenger <= '1';
else 
 updownpassenger <= '0';
 if direction_of_elevator = 1 then
 nx_state <= L4;
 elsif direction_of_elevator = 2 then
 updownpassenger <= '1';
 else
 updownpassenger <= '0';
 if direction_of_elevator = 1 then
 nx_state <= L5;< br /> elsif direction_of_elevator = 2 then
 end if;
 end if;
end if;

when L5 => 
 if (demand(4 )='1') then
 nx_state <= pr_state;
 updownpassenger <= '1';
 else 
 updownpassenger <= '0';
 if direction_of_elevator = 1 then
 nx_state <= L4;
 elsif direction_of_elevator = 2 then
 nx_state <= L1;
 else
 nx_state <= pr_state;
 end if; 
 end if; 
 when others => null; 
end case;
end process step;
end sequence;

Your code looks messy. There is a specific reason why it will not be synthesized: think carefully about the line of code immediately following here

elsif (updownpassenger = '1') then

will be executed. It will be in the sensitivity column Any input in the table will be executed after the positive or negative edge. Except for clk, it will only be executed after the negative edge. How would you design logic with this behavior? Well, your synthesizer can’t do it either.

Basically, you need to refactor the code. You need to split it into sequence and combination processes. (Combination logic is logic, and its output depends only on Because of its input, it is logic that does not contain latches or flip-flops. Sequential logic is logic that contains latches or flip-flops, but usually also contains some gates. Do not use latches-they are not a synchronous design.) Although there are many ways to code these processes, it is wise to be consistent by sticking to templates. Here are three templates, if you follow these templates, you will be provided with everything you need and make your VHDL coding life simple:

The following is a sequential logic template with asynchronous reset, all synthesis tools should understand:

process(clock, async_reset) - nothing else should go in the sensitivity list
begin
 - never put anything here
 if async_reset ='1' then - or '0' for an active low reset
 - set/reset the flip-flops here
 - ie drive the signals to their initial values
 elsif rising_edge(clock) then - or falling_edge(clock) or clk'event and clk='1' or clk'event and clk='0'
 - put the synchronous stuff here
 - ie the stuff that happens on the rising or falling edge of the clock
 end if;
 - never put anything here
end process;

The following is a sequential logic template without asynchronous reset:

process(clock) - nothing else should go in the sensitivity lis t
begin
 - never put anything here
 if rising_edge(clock) then - or falling_edge(clock) or clk'event and clk='1' or clk'event and clk= '0'
 - put the synchronous stuff here
 - ie the stuff that happens on the rising or falling edge of the clock
 end if;
 - never put anything here
end process;

This is the corresponding template for the combined process:

process(all inputs in the sensitivity list) - an ' input' is a signal either on the LHS of an assignment or a signal that is tested
begin
 - combinational logic (with complete assignment and no feedback)
end process;