I want to keep the signals in sync so that I can, for example, keep the signals in sync and The end of the pipeline correctly outputs it and manipulated pixel data after several processing stages.
I assume I want to use a shift register or something to delay the signal by the correct number of cycles in order to output Correct, but I am looking for suggestions on a good way to design this method, especially as the number of pipeline stages for different signals may be different as my design develops.
I don’t know a complete solution, but there are two partial strategies…
Interconnect components… It would be great if a component could export a generic whose value is the depth of its pipeline. Unfortunately you can’t, and it seems silly to dedicate the port to this (although It may be feasible; because it will be an integer constant, it will disappear in the composition)
If this is not possible, please pass in a generic indicating the budget of this module. If the budget cannot be met , Then assert within the module (the severity is FAILURE)… (this assertion can be checked during synthesis, at least Xilinx XST handles similar assertions)
Make the budget a hard number, if the budget is too large, then Assert if it is not equal to the actual pipeline depth, or add pipeline stages inside the module, and only assert when the budget is too small.
In this way, predictable modules can be connected, and the top level can execute pipeline algorithms to balance things (e.g. Pass the calculated constant value to the programmable delay line)
In a component…I use a process, the register is represented as an internal signal, and its name reflects its pipeline stage, exponent_1, exponent_2, exponent_3, etc. In this process, the first part describes all operations in the first cycle, the second part describes the second cycle, and so on. Usually, the “easier” path can be copied verbatim to the next pipeline stage, just to transfer They are synchronized with the critical path. This process is quite organized and easy to maintain.
I might decompose the 32-bit multiplication into 16 * 16 blocks and add some products in the pipeline. This control gives the USED ratio XST has better results…
I know that some people prefer variables in a process, and I use them for the intermediate results of the pipeline stage, but using signals I can describe the pipeline in its natural order ( Due to deferred assignment), while using variables, I will have to describe it backwards!
I am designing a VHDL video pixel data processing pipeline, involving multiple steps, including multiplication and division.
I want to keep the signals in sync so that I can for example keep Synchronize the signal and output it correctly at the end of the pipeline and manipulate the pixel data after several processing stages.
I assume I want to use a shift register or something to delay by the correct number of cycles Signal so that the output is correct, but I am looking for suggestions on a good way to design this method, especially as the number of pipeline stages for different signals, as my design develops, it may be different.
Good question.
I don’t know a complete solution, but here are two partial strategies…
Even components… It would be great if a component could export a generic whose value is the depth of its pipeline. Unfortunately you can’t, and it seems silly to dedicate the port to this (although it might be feasible; because it Will be an integer constant and it will disappear in the synthesis)
If this is not possible, please pass in a generic indicating the budget of this module. If the budget cannot be met, assert within the module (serious FAILURE)…(This assertion can be checked during synthesis, at least Xilinx XST handles similar assertions)
Make the budget a hard number. If the budget is too large, assert that if it is not equal to the actual pipeline depth, Or add a pipeline stage inside the module, and only assert when the budget is too small.
In this way, predictable modules can be connected, and the top level can execute pipeline algorithms to balance things (such as passing calculated constant values to the Programming delay line)
In a component… I use a process, the register is represented as an internal signal, and its name reflects its pipeline stage, exponent_1, exponent_2, exponent_3, etc. In this process, the first part describes All operations of the first cycle, the second part describes the second cycle, and so on. Usually, the “easier” path can be copied verbatim to the next pipeline stage, just to synchronize them with the critical path. This process Quite organized and easy to maintain.
I might decompose the 32-bit multiplication into 16 * 16 blocks and add some products. This control gives USED and gives better results than XST…< /p>
I know that some people prefer variables in a process, and I use them for the intermediate results of the pipeline stage, but using signals I can describe the pipeline in its natural order (due to delayed allocation), while using variables , I will have to describe it backwards!