The application program sets the DC cycle, offset and enable control word.
void ecrt_slave_config_dc(
ec_slave_config_t *sc, /< Slave configuration. */
uint16_t assign_activate, /*< AssignActivate word. /
uint32_t sync0_cycle, / < SYNC0 cycle time [ns]. */
int32_t sync0_shift, /< SYNC0 shift time [ns]. */
uint32_t sync1_cycle, /*< SYNC1 cycle time [ ns]. /
int32_t sync1_shift /< SYNC1 shift time [ns]. */
);
ecrt_slave_config_dc(_G_pScServo[i], 0x300, PERIOD_NS, 1000000, 0 , 0);
assign_activate is generally 0x0300, and the register is set to 0x980~0x981 to enable DC-SYNC0 synchronization signal output.
Figure 1.1 Synchronization signal register
sync0_cycle is sync0 The cycle period of the main stack is consistent with the cycle period of the periodic task of the main stack.
sync0_shift is the shift time for starting the sync0 synchronization signal.
Generally, sync1 is not used, and it can be set to 0.
After the system time between the slave stations is synchronized, it is also necessary to set the phase generated by sync0 to be consistent, so that the sync0 signal between the slave stations can be synchronized.
Set the sync start time in the void ec_fsm_slave_config_enter_dc_cycle () function of the fsm_slave_config.c file.
Figure 2.1 Set the sync cycle period to calculate the sync0 start time in the fsm_slave_config.c file The ec_fsm_slave_config_state_dc_sync_check() function.