1 ///////// ///////////////////////////////////////////////// //////////////////////
2 //The program is completed through the multiplexer MUX Bus read and write function.
3 module MuxBus(input request1,input request2,input request3,input request4,input[7:0] unit0_out,input[7 :0] unit1_out,
4 input[7: 0] unit2_out,input[7:0] unit3_out,
5 output[7:0 ] unit0_in, output[7:0< /span>] unit1_in, output[7:0] unit2_in, output[7:0] unit3_in);
6 reg[1:0] sel;
7 reg[7:0] bus;
8 always@(request1,request2,request3,request4)
9 begin
10 casex({request1,request2,request3,request4})// Note that if you want to use this priority codec here, use casex instead of case
11 4' b0001:sel=2'b00; //casex means that you don’t care about the three symbols x, z,?
12 4'b001x:sel=2'b01;
13 4'b01xx:sel=2'b10;
14 default:sel=2'b11;
15
16 endcase
17 end
18 always@(sel,unit0_out,unit1_out,unit2_out,unit3_out)
19 begin
20 case(sel)
21 2'b00:bus=unit0_out;
22 2'b01: bus=unit1_out;
23 2'b10:bus=unit2_out;
24 2'b11:bus=unit3_out;
25 endcase
26 end
27 //A careful analysis shows that the following code logically conflicts with the above code, sel is the selection signal, and it is impossible to select a certain device Then, read and write to the bus at the same time,
28 //< /span>The bus can only be in read state or write state at a certain time. If you read or write to the bus, you need to read and write control signals
29 /* [email protected](sel,bus)
30 begin
31 case(sel)< br />32 2'b00:unit0_in=bus; //At the same time, such code writing A latch unit is generated. For example, when sel=2'b01, the three devices unit0, 2, 3_in can only maintain their original values.
33 2'b01:unit1_in=bus;
34 2'b10:unit2_in=bus;
35 2'b11:unit3_in=bus;
36< /span> endcase
37 end
38 */ //The condition for no latch is to satisfy all the conditions for the same variable, not just the variables behind the case, all the conditions are written That's it, pay attention to the latching caused by the existence of different variables
39 assign< /span> unit0_in=bus;
40 assign unit1_in=bus;
41 assign unit2_in=bus;
42 assign unit3_in=bus;
43 endmodule
1 ///// ///////////////////////////////////////////////// //////////////////////////
2 //The program is completed through multiple channels The selector MUX completes the bus read and write function.
3 module MuxBus(input request1,input request2,input request3,input request4,input[7:0] unit0_out,input[7 :0] unit1_out,
4 input[7: 0] unit2_out,input[7:0] unit3_out,
5 output[7:0 ] unit0_in, output[7:0< /span>] unit1_in, output[7:0] unit2_in, output[7:0] unit3_in);
6 reg[1:0] sel;
7 reg[7:0] bus;
8 always@(request1,request2,request3,request4)
9 begin
10 casex({request1,request2,request3,request4})// Note that if you want to use this priority codec here, use casex instead of case
11 4' b0001:sel=2'b00; //casex means that you don’t care about the three symbols x, z,?
12 4'b001x:sel=2'b01;
13 4'b01xx:sel=2'b10;
14 default:sel=2'b11;
15
16 endcase
17 end
18 always@(sel,unit0_out,unit1_out,unit2_out,unit3_out)
19 begin
20 case(sel)
21 2'b00:bus=unit0_out;
22 2'b01: bus=unit1_out;
23 2'b10:bus=unit2_out;
24 2'b11:bus=unit3_out;
25 endcase
26 end
27 //A careful analysis shows that the following code logically conflicts with the above code, sel is the selection signal, and it is impossible to select a certain device Then, read and write to the bus at the same time,
28 //< /span>The bus can only be in read state or write state at a certain time. If you read or write to the bus, you need to read and write control signals
29 /* [email protected](sel,bus)
30 begin
31 case(sel)< br />32 2'b00:unit0_in=bus; //At the same time, such code writing A latch unit is generated. For example, when sel=2'b01, the three devices unit0, 2, 3_in can only maintain their original values.
33 2'b01:unit1_in=bus;
34 2'b10:unit2_in=bus;
35 2'b11:unit3_in=bus;
36< /span> endcase
37 end
38 */ //The condition for no latch is to satisfy all the conditions for the same variable, not just the variables behind the case, all the conditions are written That's it, pay attention to the latching caused by the existence of different variables
39 assign< /span> unit0_in=bus;
40 assign unit1_in=bus;
41 assign unit2_in=bus;
42 assign unit3_in=bus;
43 endmodule
