Combination hardware multiplication in Verilog

module multiply(
 output [63:0] result,
 input [31:0] a,
 input [31:0] b
 );

 assign result = a * b;
 
 endmodule

Suppose I have such a multiplier code,

module multiply(
 output [63:0] result,< br /> input [31:0] a,
 input [31:0] b
 );

 assign result = a * b;

 endmodule

This will create a lot of doors.

What better method should be used to implement a combinatorial multiplier?

The hardware multiplier is huge, you just have to live with it!

As the input bit width becomes larger, the multiplier will become larger. Therefore, if you don’t need the full 32 bits of one of the operands, reducing this size to the minimum will reduce The size of the resulting hardware.

If you multiply by a fixed number, I think the compiler can make some optimizations to limit the size of the hardware. Or you can use a different encoding scheme for the fixed number, such as CSD, This will reduce the number of adders in the multiplier, thereby further reducing its area.

If you need a large number of multipliers and have a fast clock, then you can reuse a single hardware multiplier for multiple calculations. This Means to write some control/pipeline logic to arrange your multiplication, you may need some memory, but it can save the whole area. In this case, you will design a mini-DSP data path.