Automation – Is there any recommended approach from a moving module port connection?

I am trying to understand or study the best practices of ASIC design in verilog. I am developing a medium-sized Block, there are about 20 sub-modules (each line ~1000 lines of code). It is hard work to manually instantiate all the sub-modules and make port connections to create the top-level RTL.

I want to write A script to automate this operation. As long as we can define the input/output of all sub-modules and how each sub-module is connected to each other, it won’t be too difficult to automatically generate the top layer. But I don’t have enough expertise in design automation. I Want to know if someone can give me some instructions on how to start.

>Are there any open source tools to achieve what I want to do? I haven’t found anything so far.
>Is there any standardized method to generate such synthesizable code?

I really appreciate any kind of comments or suggestions.

Depending on the text editor you use, you may be able to use some pre-existing Tools. Assuming you follow certain naming conventions, Emacs add-ons support automatic instantiation and connection of signals:

http://www.veripool.org/wiki/verilog-mode/Verilog -mode_veritedium

For vim users there, there are some plugins that allow the use of Emacs scripts, for example:

http://www.vim.org/scripts/script.php?script_id =1875