Chapter 6 Bus

1. Bus overview
   1. Basic concept of bus

      Bus is more connected A non-cutting information transmission line is a transmission medium shared by each non-cutting. Time sharing and sharing are two characteristics of the bus.

      Time sharing means that only one component is allowed to send information to the bus at a time. If there are multiple components in the system, they can only send information to the bus in a time-sharing manner.

      Sharing means that multiple components can be mounted on the bus, and each component can be exchanged with each other The information can be shared in time sharing through this group of lines. Only one component is allowed to send information to the bus at the same time, but multiple non-cutting devices can receive information from the bus at the same time.

      1. The transmission cycle of the bus. Refers to the time required for the CPU to access the memory or I/O port once through the bus, including the bus application phase, addressing phase, transmission phase and end phase.
      2. Bus width.
      3. bus characteristics. Machine characteristics, electrical characteristics, functional characteristics, time characteristics.
   2. Classification of buses
      1. According to the data transmission mode, it can be divided into parallel transmission bus and serial transmission bus.
      2. According to the use of the bus can be divided into Computer bus, measurement and control bus, etc.
      3. can be divided into slices according to different connecting parts Internal bus, system bus, communication bus, etc.
         1. On-chip bus: The bus inside the chip.
         2. System bus: the information transmission line connecting the five components . According to the different transmission information of the system bus, it can be divided into: data bus, address bus and control bus.
            1. Data bus: used to transmit the Information data, he is a two-way transmission bus.
            2. Address bus: One-way transmission bus. It is mainly used to indicate the address of the source data or destination data on the data bus in the main memory unit or the address of the I/O device.
            3. Control bus: Because the data bus and address bus are owned If the components are shared, how to enable each component to have the right to use the bus at different times also needs to be completed by the control bus. Therefore, the control bus is a transmission line used to send out various control signals.
         3. Communication bus: Used for communication between computer systems or between computer systems and other systems. Divided into serial communication and parallel communication.
   3. Bus composition and performance indicators
      1. The composition of the bus: Usually a set of control lines, a set of data lines, and a set of address lines. Some buses do not have a separate address line, and address information is also transmitted through the data line, which is called data line and address line multiplexing.
      2. Performance Metrics
         1. bus width. Usually refers to the number of data buses
         2. Bus bandwidth. The number of bits of data transmitted on the bus per unit time.
      3. Bus multiplexing.
      4. Number of signal lines. The sum of the number of buses in the address bus, data bus and control bus 3.
   4. The structure of the bus
      1. Single bus structure

         Link the CPU, main memory, and I/O devices on a set of buses, allowing direct exchange of information between I/O devices, between I/O devices and CPU, or between I/O devices and main memory. The structure is simple, and it is easy to expand the external equipment. The disadvantage is that all the transmissions are through this group of shared buses, and two or more components are not allowed to transmit information to the bus at the same time, which is inefficient.

         Features: Since the I/O device and the main memory share one address line, the main The memory and I/O devices are addressed uniformly, and the CPU can access external devices like memory.

      2. Dual bus structure< /span>

         Features: I/O devices with lower speed are separated from a single bus to form The main memory bus is separated from the I/O bus.

      3. Three-bus structure< /span>

         Compared with the dual-bus structure, the three-bus structure adds a small path (DMA bus), Specially used for direct exchange of information between I/O high-speed devices and main memory. In the three-bus structure, only one type of bus can be used at any time.

2. Bus Arbitration

   Determine the devices that can gain control when competing for bus control at the same time

   1. Centralized arbitration mechanism
      1. Chain query method
         1. Priority discrimination method: The closer to the bus, the higher the priority, and vice versa, the lower.
         2. Benefits : Only 3 control lines can realize bus control according to a certain priority. The structure is simple and easy to expand.
         3. Disadvantages : Sensitive to circuits; when components with high priority frequently request to use the bus, components with lower priority will not be able to use the bus for a long time.
      2. Counter query method
         1. Priority discrimination method: When the bus controller receives the bus request signal and judges that the bus is not busy, the counter starts counting, and the count value is sent to each component through a set of address lines. When the count value on the address line is consistent with the address of the device requesting to use the bus, the device obtains bus control. At the same time, the germplasm counter counts and queries work.

            The counter has two counting methods: 1. Each time the counter arbitrates, it starts from “0”. At this time, once the device After the limited order is fixed, the priority of the device will be arranged in descending order of 0,1,2,…,n and can never be changed; 2. The counter can also start counting from the end of the last time, and all devices use the bus at this time Are equal in priority.

         2. Advantages: Each device has a connection sequence It can be changed, and it is not as sensitive to circuit faults as the chain query method.
         3. Disadvantages : Increased control time, control is also more complicated than chain query.
      3. Independent request method
         1. Priority discrimination method: When the components on the bus need to use the bus, the bus request signal is sent through the respective bus request line and queued in the bus controller. When the bus controller decides to approve the request of a certain component in a certain limited order, it sends a bus response signal to the component, and the component receives the secondary signal and obtains the right to use the bus and starts to transmit data.
         2. Benefits : The response time is very fast, and the control of the priority order is quite flexible.
         3. Disadvantages : There are many control lines (n devices need 2n control lines), and the bus control is more complicated.
   2. Distributed arbitration mechanism

      No central arbiter is needed. Each main module has its own arbitration number and arbiter, and multiple arbiters compete to use the bus. When they have a bus to request, they send the arbitration number of their respective location to the shared arbitration bus, and each arbiter will compare the arbitration number obtained from the arbitration bus with its own arbitration number. If the priority of the number on the arbitration bus is high, its bus request will not be responded to, and its arbitration number will be revoked. Finally, the arbitration number of the winner remains on the arbitration bus.

3. Bus operation and timing
   1. bus The concept of cycle
      1. application for allocation stage. The main module that needs to use the bus will grant a certain applicant the right to use the bus to determine the next transmission cycle through bus arbitration.
      2. Find Address stage. The master module that has obtained the right of use sends the address of the slave module to be accessed this time and related commands through the bus to start the slave module participating in this transmission.
      3. Send Data stage. The master module and the slave module exchange data. The data is sent from the source module and flows into the destination module via the data bus.
      4. end stage. The relevant information of the main module is removed from the system bus, giving up the right to use the bus.
   2. Sync timing method
   3. Asynchronous timing method
      1. Non-interlocking method
      2. Semi-interlocking method
      3. Full interlocking method
4. Bus standard
   1. System bus standard
      1. ISA
      2. EISA
      3. VESA
      4. PCI
      5. PCI-E

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   Device bus standard
   1. IDE
   2. AGP
   3. USB
   4. < span style="font-size: 10pt">SATA

Overview of the bus

Basic concept of the bus< /span>

The classification of the bus

The bus Composition and performance indicators

The structure of the bus

Bus arbitration

Centralized arbitration mechanism

Distributed arbitration mechanism

Bus operation and timing

Synchronous timing method

Asynchronous timing method

Bus standard

Bus overview

Basic concept of the bus

The transmission cycle of the bus. Refers to the time required for the CPU to access the memory or I/O port once through the bus, including the bus application phase, addressing phase, transmission phase and end phase.

Bus width.

Bus characteristics. Machine characteristics, electrical characteristics, functional characteristics, time characteristics.

Classification of buses

According to the data transmission mode, it can be divided into parallel transmission bus and serial transmission bus.

According to the use range of the bus, it can be divided into computer bus, measurement and control bus and so on.

According to the different connecting parts, it can be divided into on-chip bus, system bus, communication bus and so on.

On-chip bus: The bus inside the chip.

System bus: connect the information transmission line between the five major components. According to the different transmission information of the system bus, it can be divided into: data bus, address bus and control bus.

Data bus: used to transmit information and data between various functional components, it is a two-way transmission bus.

Address bus: One-way transmission bus. It is mainly used to indicate the address of the source data or destination data on the data bus in the main memory unit or the address of the I/O device.

Control bus: Since the data bus and address bus are shared by all components, how to make each component have the right to use the bus at different times , It also needs a control bus to complete, so the control bus is a transmission line used to send out various control signals.

Communication bus: used for communication between computer systems or between computer systems and other systems. Divided into serial communication and parallel communication.

Bus composition and performance indicators

The composition of the bus: Usually a set of control lines, a set of data lines, and a set of address lines. Some buses do not have a separate address line, and address information is also transmitted through the data line, which is called data line and address line multiplexing.

performance indicators

Bus width. Usually refers to the number of data buses

bus bandwidth. The number of bits of data transmitted on the bus per unit time.

Bus multiplexing.

Number of signal lines. The sum of the number of buses in the address bus, data bus and control bus 3.

The structure of the bus

Single bus structure

Double Bus structure

Three-bus structure

Bus arbitration

Centralized arbitration mechanism

Chain query method

< span style="font-size: 10pt">Priority discrimination method: The closer to the bus, the higher the priority, and vice versa, the lower.

Advantages: Only 3 control lines are needed to press a certain The priority level realizes the bus control, the structure is simple, and it is easy to expand.

Disadvantages: Sensitive to circuits; when high priority components are frequent When requesting to use the bus, components with lower priority will not be able to use the bus for a long time.

Counter query method

Priority discrimination method: When the bus controller receives the bus request signal and judges that the bus is not busy, the counter starts counting, and the count value passes through a set of addresses The line is sent to each component. When the count value on the address line is consistent with the address of the device requesting to use the bus, the device obtains bus control. At the same time, the germplasm counter counts and queries work.

Advantages: The connection sequence of each device can be changed, and the Circuit failure is not as sensitive as the chain query method.

Disadvantages: Increased control time, and control is better than chain query complex.

Independent request method

Priority discrimination method: When the components on the bus need to use the bus, the bus request signal is sent through the respective bus request line, and the bus controller In line. When the bus controller decides to approve the request of a certain component in a certain limited order, it sends a bus response signal to the component, and the component receives the secondary signal and obtains the right to use the bus and starts to transmit data.

Pros: Fast response time, control of priority order Quite flexible.

Disadvantages: There are many control lines (n devices require 2n Control line), bus control is more complicated.

Distributed arbitration mechanism

Bus operation and timing

The concept of bus cycle

application allocation stage. The main module that needs to use the bus will grant a certain applicant the right to use the bus to determine the next transmission cycle through bus arbitration.

Addressing phase. The master module that has obtained the right of use sends the address of the slave module to be accessed this time and related commands through the bus to start the slave module participating in this transmission.

Transfer data stage. The master module and the slave module exchange data. The data is sent from the source module and flows into the destination module via the data bus.

End stage. The relevant information of the main module is removed from the system bus, giving up the right to use the bus.

Sync timing method

Asynchronous timing method

No Interlocking method

Semi-interlocking method

< p>Full interlocking method

Bus standard

System bus standard

ISA

EISA

AGP

USB

< span style="font-size: 10pt">SATA