>Why must the data be aligned (on a 2-byte/4-byte/8-byte boundary)? What I suspect here is that when the CPU has address lines Ax Ax-1 Ax-2… A2 A1 A0, it is likely to address memory locations sequentially. So why do you need to align data at a specific boundary?
>How to find the alignment requirements when compiling code and generating executable files?
>For example, if the data alignment is on a 4-byte boundary, does that mean that each consecutive byte is located at a modulo-4 offset? What I suspect is that if the data is 4-byte aligned, does that mean if one byte is 1004 then the next byte is 1008 (or 1005)?
For many Instructions, Intel CPU can perform access to non-word boundaries, but since the internal CPU performs two memory accesses and one mathematical operation to load a word, there is a performance penalty. If you are performing byte reads, alignment is not applied. /p>
Some CPUs (ARM or Intel SSE instructions) require aligned memory and have undefined operations when making unaligned accesses (or throwing exceptions). They do not implement more complex load/store Subsystem to save a lot of silicon space.
The alignment depends on the CPU word size (16, 32, 64 bit), or in the case of SSE, the SSE register size (128 bit).
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For your last question, if you only load one data byte at a time, most CPUs do not have alignment restrictions (some DSPs do not have byte-level instructions, but you may not encounter one). /p>
Please forgive me, if you think this has been answered countless times, but I need to answer the following questions!
>Why must the data be aligned (on a 2-byte/4-byte/8-byte boundary)? What I suspect here is that when the CPU has address lines Ax Ax-1 Ax-2… A2 A1 A0, it is likely to address memory locations sequentially. So why do you need to align data at a specific boundary?
>How to find the alignment requirements when compiling code and generating executable files?
>For example, if the data alignment is on a 4-byte boundary, does that mean that each consecutive byte is located at a modulo-4 offset? What I suspect is that if the data is 4-byte aligned, does that mean if one byte is 1004 then the next byte is 1008 (or 1005)?
The CPU is word-oriented, not byte-oriented. In a simple CPU, the memory is usually configured to return one word per address strobe (32-bit, 64-bit, etc.), where the two (or more) address lines at the bottom are usually unrelated bits.
For many instructions, Intel CPU can perform access to non-word boundaries, But because the internal CPU performs two memory accesses and a mathematical operation to load a word, there is a performance penalty. If you are performing byte reads, alignment is not applied.
Some CPUs (ARM or Intel SSE instructions) require aligned memory and have undefined operations when making unaligned accesses (or throwing exceptions). They save a lot of silicon space by not implementing more complex load/store subsystems.
The alignment depends on the CPU word size (16, 32, 64 bit), or in the case of SSE, the SSE register size (128 bit).
For your last question, if You only load one data byte at a time, and most CPUs have no alignment restrictions (some DSPs do not have byte-level instructions, but you may not encounter one).