My first question is MMU Does it handle everything between CPU and RAM. Is this true? From what you can read on Wikipedia, I would say this:
A memory management unit (MMU), sometimes called paged memory
management unit (PMMU ), is a computer
hardware component responsible for
handling accesses to memory requested
by the CPU.
If this is the case, then how to tell MMU I want Get 8 bytes, 64 or 128 bytes, for example? How about writing?
If this is not the case, I guess MMU just converts virtual addresses to physical addresses?
What happens when the MMU detects what we call a page fault? I think it must tell the CPU so that the CPU loads the page itself from disk, or can the MMU do this?
Thank you
I will try to answer your questions one by one, but please note that you can put the manual on the OS course or the introductory computer architecture course.
MMU is composed of some hardware logic and status. The purpose is actually to generate a physical address and provide/receive data to the memory controller. In fact, the work of memory conversion is a work handled by a cooperative hardware and software (OS) mechanism (at least in modern PCs). Once the physical address is obtained , The CPU basically does its job and now sends the address to the bus, which is connected to the actual memory chip at some point. In many systems, this bus is called the front side bus (FSB), the latter It is connected to the memory controller again. The controller obtains the physical address provided by the CPU and uses it to interact with the DRAM chip, and finally extracts the bits in the correct row and column of the memory array. Then the data is sent back to the CPU, and the CPU can now It operates. Please note that I do not include the cache in this description.
So no, the MMU does not directly interact with the RAM, I think you use it to represent the physical DRAM chip. You cannot tell the MMU what you want To 8 bytes, or 24 bytes, or whatever, you can only provide an address. The number of bytes you get depends on the machine you are in and whether it is byte-addressable or word-addressable. /p>
Your last question prompted me to remind you: The MMU is actually part of the CPU – it is on the same chip (although this is not the case).
Now, let’s take the page Take the error as an example. Assuming our user-level application wants to set someAddress = 10 as you said, I will adopt it gradually. Assuming someAddress is 0xDEADBEEF, let’s ignore the cache for now.
1) Application Issue a store instruction to 0xsomeAddress, which may look like in x86
mov %eax, 0xDEADBEEF
where 10 is the value in the eax register.
mov %eax, 0xDEADBEEF
p>
2) In this case, 0xDEADBEEF is a virtual address that must be translated. In most cases, virtual-to-physical address translation will be available in a hardware structure called the translation lookaside buffer (TLB), which This conversion will be provided to us very quickly. Normally, it can be completed in one clock cycle. If the conversion is in the TLB, called a TLB hit, it can continue to execute immediately (i.e., the physical address corresponding to 0xDEADBEEF and the value 10 is Send to the memory to be written Controller).
3) However, we assume that the translation is not available in the TLB (called a TLB miss). Then we have to find the translation in the page table, which is in memory Structures, whose structure is defined by the hardware and managed by the OS. They only contain entries that map virtual addresses to physical addresses (more precisely, virtual page numbers to physical page numbers). But these structures also exist in memory, so Must have an address! The hardware contains a special register called cr3, which contains the physical address of the current page table. We can use our virtual address to index to this page table, so the hardware gets the value in cr3, calculates the address by adding an offset, and then Go to memory to get the page table entry (PTE). This PTE will (hopefully) contain the physical address corresponding to 0xDEADBEEF, in this case we put this mapping in the TLB (so we don’t have to traverse the page table again) and Continue our way.
4) But oh no! What if there is no PTE in the page table of 0xDEADBEEF? This is a page fault, this is where the operating system comes into play. The PTE we get from the page table exists because it is (let us assume) a valid memory address to access, but the operating system has not yet created a VA for it- > PA mapping, so it will be set a little bit to indicate that it is invalid. The hardware is programmed in such a way: when it sees the invalid bit during access, it generates an exception, in this case a page fault.
5) The exception causes the hardware to call the operating system by jumping to a well-known location-a piece of code called a handler. There can be many exception handlers, and the page fault handler is one of them. Page fault handling The program will know the address that caused the error because it is stored in some register, so it will create a new mapping for our virtual address 0xDEADBEEF. It will allocate a free page of physical memory and then say “between VA x and VA y All virtual addresses will be mapped to an address in this newly allocated physical memory page” to achieve. 0xDEADBEEF will be somewhere in the range, so the mapping now safely exists in the page table, and we can restart to cause Page fault instruction (mov).
6) Now, when we browse the page table again, we will find a mapping, and the PTE we extracted will have a good physical address, that is, we want to store The address. We provide a value of 10 for the memory controller, and we are done!
Caching will change this game, but I hope this can illustrate how paging works. Again, looking at some OS/computer architecture books will help you. I hope this is clear.
I want to understand how the operating system works when we want to assign some value to a specific virtual memory address.
My first question is Does the MMU handle everything between the CPU and RAM. Is this true? From what you can read on Wikipedia, I would say this:
A memory management unit (MMU), sometimes called paged memory
management unit (PMMU ), is a computer
hardware component responsible for
handling accesses to memory requested
by the CPU.
If this is the case, then how to tell MMU I want Get 8 bytes, 64 or 128 bytes, for example? How about writing?
If this is not the case, I guess MMU just converts virtual addresses to physical addresses?
What happens when the MMU detects what we call a page fault? I think it must tell the CPU so that the CPU loads the page itself from disk, or can the MMU do this?
Thank you
The swallowed world of bliss,
I will try to answer your questions one by one, But please note that you can put the manual on an OS course or an introductory computer architecture course.
MMU consists of some hardware logic and state, and its purpose is actually to generate a physical address and send it to the memory controller Provide/receive data. In fact, the work of memory conversion is a work handled by a cooperative hardware and software (OS) mechanism (at least in modern PCs). Once the physical address is obtained, the CPU basically does its job , Now the address is sent to the bus, which is connected to the actual memory chip at some point. In many systems, this bus is called the front side bus (FSB), which in turn is connected to the memory controller. This controller gets the CPU Provide the physical address and use it to interact with the DRAM chip, and finally extract the bits in the correct row and column of the memory array. Then send the data back to the CPU, and the CPU can now operate on it. Please note that I am in this description Cache is not included.
So no, MMU does not directly interact with RAM, I think you use it to represent physical DRAM chips. You cannot tell MMU that you want 8 bytes, or 24 bytes, Or whatever, you can only provide one address. The number of bytes you get depends on the machine you are in and whether it is byte-addressable or word-addressable.
Your last question prompted Let me remind you: MMU is actually part of the CPU-it is on the same chip (although this is not the case).
Now, let’s take the page fault as an example. Suppose our user-level application wants Set someAddress = 10 like you said, and I will adopt it gradually. Assuming that someAddress is 0xDEADBEEF, let’s ignore the cache for now.
1) The application issues a store instruction to 0xsomeAddress, which may look like in x86 Like
mov %eax, 0xDEADBEEF
where 10 is the value in the eax register.
2) In this case , 0xDEADBEEF is a virtual address that must be translated. In most cases, virtual-to-physical address translation will be available in a hardware structure called a translation lookaside buffer (TLB), which will provide us with this translation very quickly. Generally, It can be completed in one clock cycle. If the conversion is in the TLB, called a TLB hit, the execution can continue immediately (i.e., the physical address corresponding to 0xDEADBEEF and the value 10 are sent to the memory controller to be written ).
3) However, we assume that the translation is not available in the TLB (called a TLB miss). Then we have to find the translation in the page table, the page table Are structures in memory whose structure is defined by the hardware and managed by the OS. They only contain entries that map virtual addresses to physical addresses (more precisely, virtual page numbers to physical page numbers). But these structures also exist in In memory, so there must be an address! The hardware contains a special register called cr3, which contains the physical address of the current page table. We can use our virtual address to index to this page table, so the hardware gets the value in cr3, calculates the address by adding an offset, and then Go to memory to get the page table entry (PTE). This PTE will (hopefully) contain the physical address corresponding to 0xDEADBEEF, in this case we put this mapping in the TLB (so we don’t have to traverse the page table again) and Continue our way.
4) But oh no! What if there is no PTE in the page table of 0xDEADBEEF? This is a page fault, this is where the operating system comes into play. The PTE we get from the page table exists because it is (let us assume) a valid memory address to access, but the operating system has not yet created a VA for it- > PA mapping, so it will be set a little bit to indicate that it is invalid. The hardware is programmed in such a way: when it sees the invalid bit during access, it generates an exception, in this case a page fault.
5) The exception causes the hardware to call the operating system by jumping to a well-known location-a piece of code called a handler. There can be many exception handlers, and the page fault handler is one of them. Page fault handling The program will know the address that caused the error because it is stored in some register, so it will create a new mapping for our virtual address 0xDEADBEEF. It will allocate a free page of physical memory and then say “between VA x and VA y All virtual addresses will be mapped to an address in this newly allocated physical memory page” to achieve. 0xDEADBEEF will be somewhere in the range, so the mapping now safely exists in the page table, and we can restart to cause Page fault instruction (mov).
6) Now, when we browse the page table again, we will find a mapping, and the PTE we extracted will have a good physical address, that is, we want to store The address. We provide a value of 10 for the memory controller, and we are done!
Caching will change this game, but I hope this can illustrate how paging works. Again, looking at some OS/computer architecture books will help you. I hope this is clear.